Conventional microelectronics processes for forming an opening such as a trench, via, or plug in a dielectric layer include depositing the dielectric layer, patterning and then etching the dielectric layer to form the opening or a trench in the dielectric layer, depositing an electrically conductive material (e.g., tungsten—W or copper—Cu) in the opening, and then planarizing the tungsten film down to the dielectric material to form a substantially planar surface. Ideally, the dielectric layer and the electrically conductive material are smooth, planar, and substantially flush with each other.
In FIGS. 1A-1C, a conventional structure 100 depicts a dielectric layer 107 (e.g., SiO2) and an electrically conductive structure 110 (e.g., tungsten—W or copper—Cu) positioned in a trench 107s formed in the dielectric layer 107. Although a trench structure is depicted, the electrically conductive structure could be a via, a plug, or the like. Trench 107s has a width along an X axis, a height along a Z axis, and a length along a Y axis (denoted 104). Here, the dielectric layer 107 has previously been patterned and etched to form the trench 107s, an electrically conductive material has been deposited in the trench 107s (e.g., using CVD, sputtering, or the like), and then the dielectric layer 107 and electrically conductive material have been planarized to form planar surface 107t and electrically conductive structure 110 positioned in the trench 107s. However, an upper surface of the electrically conductive structure 110 is recessed 107r below the planar surface 107t and the upper surface includes surface roughness 110r and seams 110s (also referred to as voids or divots). The recessed upper surface 107r is the result of the selective polishing slurry used in chemical mechanical polishing (CMP) process. As the CMP process is applied to those materials, the slurry used is selective to the electrically conductive material (e.g., tungsten—W or copper—Cu) used for the electrically conductive structure 110 than to the dielectric layer 107 (e.g., SiO2) such that the electrically conductive material that fills the trench 107s is removed at a faster rate (e.g., polished faster) than the dielectric layer 107 and becomes recessed 107r below the planar surface 107t. 
In FIGS. 1A-1C, lateral grains 110g grow inward from the sidewall surfaces of the trench 107s towards the center of the electrically conductive structure 110. The lateral grains cause formation of the aforementioned seams 110s that contribute to the surface roughness 110r. In some applications, prior to depositing the material for the electrically conductive structure 110, the sidewall surfaces of the trench 107s can be lined with a thin layer of an electrically conductive material 111 (e.g., titanium nitride—TiN and/or titanium—Ti) as depicted in structure 100a in FIG. 1B. However, the presence of the liner 111 does not remedy the aforementioned recess 107r, surface roughness 110r, or seams 110s; therefore, for purposes of discussion, the liner will not be depicted in subsequent FIGS.
In FIGS. 1A-1C, the dielectric layer 107, the electrically conductive structure 110, and other structures in those figures can be fabricated back-end-of-the-line (BEOL) directly on top of a substrate 150 (e.g., a silicon wafer) that includes circuitry 181 (e.g., CMOS circuitry) that is fabricated front-end-of-the-line (FEOL). The circuitry 181 is electrically coupled 185 with BEOL structure 103 via FEOL conductive structure 101. Here, because the FEOL structure is fabricated first and the BEOL structure is fabricated on top of the FEOL structure, the FEOL structure is depicted as being disposed along the −Z axis and the BEOL structure is depicted disposed along the +Z axis. For purposes of illustration, the FEOL structure may not be shown in FIGS. 1D-1O.
In FIG. 1D, a layer of material 112 (e.g., an electrically conductive adhesion layer of titanium nitride—TiN) is deposited 109c on the dielectric layer 107 and on the surface 110r of the electrically conductive structure 110. Due to the aforementioned seams 110s and the surface roughness 110r, the layer 112 fills in 110g the seams 110s and conformally covers surfaces 110r and 107t such that the surface roughness 110r is approximately replicated 112t in portions of the layer 112 that cover surface 110r of the electrically conductive structure 110. Although layer 112 is deposited to a thickness of t1 as measured from surface 107t, the actual thickness varies (i.e., 112t) in those portions of the layer 112 that cover the electrically conductive structure 110 due to the surface roughness 110r. Therefore, subsequently layers of thin film materials that are deposited on the layer 112 will not be substantially planar due to the roughness 112t in layer 112 that can be replicated in the subsequently deposited thin film layers.
Turning now to FIG. 1E, a layer of electrically conductive material 114 (e.g., for an electrode) is deposited 114d on the layer 112 and the surface roughness 112t is approximately replicated 114t in the layer 114. In FIG. 1F, an adhesion or glue layer 116 (e.g., an electrically conductive adhesion layer of titanium nitride—TIN) is deposited on the layer 114 with surface irregularities 114t approximately replicated 116t in the layer 116. Following the deposition of layer 116, a layer of oxide 118 is deposited on the layer 116 and the layer 118 is patterned with a layer of mask material (e.g., lithographically patterned photoresist) to form etch mask 119. Next, the layer 118 is etched 119e to form a hard etch mask 118m depicted in FIG. 1G. Etch mask 119 can subsequently be removed using a stripping or ashing process. In FIGS. 1G through 1H, the hard mask 118m is used to etch 121e layers 116, 114, and 112 down to the surface 107t of oxide layer 107 using multiple etch steps (not shown) to form discrete stacks of thin film materials over the electrically conductive structures 110 in trenches 107s. It should be noted that the layers 116, 114, and 112 still retain the aforementioned surface roughness.
In FIG. 1I, a layer of dielectric material (e.g., SiO2) 123 is deposited 125d over the structures depicted in FIG. 1H and in FIGS. 1J through 1K, a multi-step CMP process is used to remove material and to planarize the layers down to a plane 120p, which results in recessing the oxide 123 down to a plane 122p to completely remove the layer 116. In FIG. 1K, after the CMP process is completed, the layer 114 is not planar with the layer 123 and includes surface roughness 114t. Here, a slurry used in the CMP process for removing layer 116 may have been more selective to the oxide 123 than the material for layer 114 (e.g., platinum—Pt) such that the oxide 123 is polished faster than the layer 114 resulting in the oxide 123 being recessed below the layer 114 by an approximate distance ΔP as measured from a planar upper surface 123t to the highest point of the rough portions 114t of the layer 114. As was described above, the surface roughness 1141 can be replicated in subsequently deposited thin film layers.
In FIG. 1L, two layers of thin film materials are deposited 131d on the structure depicted in FIG. 1K, a layer 126 and much thinner layer 128. Portions of the layers 126 and 128 are operative to form a memory element in a memory cell. In the example depicted, the layer 126 can be one or more layers of a conductive metal oxide (CMO) and the layer 128 can be a very thin layer of an electronically insulating material (e.g., YSZ) that can be approximately 50 Å or less in thickness. Here, surface roughness 1141 is replicated 1321 in layers 126 and 128 and causes variations in thickness of those layers such that along layer 128 a thickness tB2 is thinner than a thickness tB1 and along layer 126 a thickness tC2 is thinner than a thickness tC1. Portions of the layers 126 and 128 that are positioned over electrodes 114 form part of a memory element and the electrical characteristics of the memory element and performance of the memory element can be adversely affected by the aforementioned variations in layer thickness created by surface roughness (114t, 132t). For example, thickness variations in layer 128 can result in pinholes, shorts, variations in tunneling conduction, and non-uniform cell characteristics among memory cells in a memory array structure. Although only two layers (126, 128) are depicted, if additional layers are deposited above the layer 128, then the surface roughness can be replicated in those additional layers as well.
Turning now to FIG. 1M, a top down SEM image 160 of platinum (Pt) bottom electrodes (BE) 114 depicted in cross-sectional view in FIG. 1K illustrates the BE 114 including the surface roughness 114t that approximately replicates the surface roughness 112t (e.g., in FIG. 1E) and voids or seams in encircled areas that are due to the seams 110s in the electrically conductive structure 110 in the trenches 107s (e.g., in FIG. 1K).
Moving on to FIG. 1N, an electron microscope image 170 illustrates a cross-sectional image of the effects of surface roughness (112t, 114t, etc.) and seams 110s on the layers (126, 128). Here, lateral grains 110g cause seams 110s and surface roughness in layers 112 and 114. The distance ΔP between the surface of 123 and the highest portion of layer 114 is clearly evident. Consequently, the surface roughness in layer 114 is replicated in the layers 126 and 128. The layer 128 is so thin (e.g., <50 Å) that it can not be seen in image 170; however, the layer 128 follows the profile of layer 126 as depicted in the encircled region for layers (126, 128).
In FIG. 1O, an array current map depicts one consequence of the surface defects (e.g., surface roughness and seams) is non-uniformity in device parameters. Here, a plot 180 of current in nA for memory cells at different X and Y addresses in a memory array (e.g., a two-terminal cross-point array) depicts several memory cells with cell currents during data operations (e.g., read or write operations) that have currents 184 that are well in excess of 200 nA as depicted in the plot 180 and in the encircled area 186 in legend 188. As can be seen, some of the cells have currents in the 300 nA to 450 nA range. The excessive currents are indicative of memory cells (e.g., leaky cells) having high current leakage (e.g., 126 and 128) during data operations. Sense amp circuitry can be used for generating logic levels by determining a magnitude of a read current flowing through a memory cell during a read operation. Typically, one magnitude of a read current is indicative of a logic “0” (e.g., a high resistance programmed state) and another magnitude of read current is indicative of a logic “1” (e.g., a low resistance erased state). For leaky cells, the high magnitude of the leakage current prevents the sense amp circuitry from determining the read current of the cell being read because the magnitude of the leakage current is exceeds the range of acceptable values for read currents. High leakage currents can also interfere with the ability of the sense amp circuitry to determine the read current from other memory cells in the array.
Based on the foregoing FIGS. 1A-1N, it is preferable to reduce or eliminate surface roughness in thin film layers so that the layers that form the active portion of the memory element are planar surfaces that are uniformly thick across the entire memory array. It is also desirable to reduce the number of processing steps required to form the planar layers (e.g., the number of CMP processes). Fewer processing steps can reduce fabrication costs and can result in fewer defects and/or increased device yield.
There are continuing efforts to improve microelectronics fabrication processes for thin films.
Although the above-described drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the drawings are not necessarily to scale.